WTA-waveform-based timing analysis for deep submicron circuits

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 2002, Pages 625-631

  McMurchie, Larry ^a   Sechen, Carl ^a  

^a University of Washington   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CIRCUIT SIMULATION; DEEP SUBMICRON CIRCUITS; STATIC TIMING ANALYZERS; WAVEFORM BASED TIMING ANALYSIS;

ALGORITHMS; APPLICATION SPECIFIC INTEGRATED CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTATIONAL COMPLEXITY; COMPUTER SIMULATION; ELECTRIC NETWORK ANALYZERS; ELECTRIC POTENTIAL; ELECTRIC WAVEFORMS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; PERT;

ELECTRIC NETWORK ANALYSIS;

EID: 0036911948     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/774572.774665     Document Type: Conference Paper

References (9)

1. J. Ousterhout, "A Switch-Level Timing Verifier for Digital MOS VLSI," IEEE Trans. On Computer-Aided Design, Vol. CAD-4, No. 3, July 1985, pp. 336-349.
2. N. Jouppi, "Timing Analysis and Performance Improvement of MOS VLSI Designs," IEEE Trans. On Computer Aided Design, Vol. CAD-6, No. 4, July 1987, pp. 650-665.
3. S. Hwang, Y. Kim and A. Newton, "An Accurate Delay Modeling Technique for Switch-level Timing Verification," Proc. of the 23rd Design Automation Conference, June 1986, pp. 227-233.
4. M. Dagenais, S. Gaiotti and N. Rumin, "Transistor-Level Estimation of Worst-Case Delays in MOS VLSI Circuits," IEEE Trans. On Computer-Aided Design, Vol 11, No. 3, March 1992, pp. 384-395.
5. V. Narayanan, B. Chappell, and B. Fleischer, "Static Timing Analysis for Self-Resetting Circuits," 1996 IEEE/ACM Intl. Conf. On Computer-Aided Design, 1996 pp. 119-126.
6. D. Blaauw, V. Zolotov, S. Sundareswaran, C. Oh, and R. Panda, "Slope Propagation in Static Timing Analysis," 2000 IEEE/ACM Intl. Conf. On Computer-Aided Design, 2000 pp. 338-343.
7. M. Desai and Y. Yen, "A Systematic Technique for Verifying Critical Path Delays in a 300 MHz Alpha CPU Design Using Circuit Simulation," Proc. of the 33rd Design Automation Conference, 1996.
8. A. Kayssi, K. Sakallah, and T. Mudge, "The Impact of Signal Transition Time on Path Delay Computation," IEEE Trans. on Circuits and Systems -II: Analog and Digital Signal Processing, Vol. 40, No. 5, May 1993. pp. 302-309.
9. S. Sun, D. Du and H Chen, "Efficient Timing Analysis for CMOS Circuits Considering Data Dependent Delays," IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, Vol. 17, No. 6, June 1998, pp. 546-552.