An accurate delay modeling technique for switch-level timing verification

Proceedings - Design Automation Conference

Volumn , Issue , 1986, Pages 227-233

  Hwang, Seung H ^a   Kim, Young H ^a   Newton, A R ^a  

^a UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER AIDED DESIGN; ECONOMIC AND SOCIAL EFFECTS; TIMING CIRCUITS;

ACCURATE DELAY MODELS; ACCURATE TIMING; DELAY ANALYSIS; DELAY MODELING; MOS CIRCUITS; SPEED ACCURACY; SWITCH-LEVEL TIMING; TRADE OFF;

DELAY CIRCUITS;

EID: 84909753608     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/DAC.1986.1586093     Document Type: Conference Paper

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