Design methodology for IBM ASIC products

IBM Journal of Research and Development

Volumn 40, Issue 4, 1996, Pages 387-405

  Engel, J J ^a,b,c,d   Guzowski, T S ^a,b,c,e   Hunt, A ^a,b,c,f   Lackey, D E ^a,b,c,g,h,i   Pickup, L D ^a,b,c,j   Proctor, R A ^a,b,c,k   Reynolds, K ^a,b   Rincon, A M ^c   Stauffer, D R ^c  

^a IBM MICROELECTRONICS   (United States)

^b IBM   (United States)

^c New York Institute of Technology ^*

^d NEW YORK INSTITUTE OF TECHNOLOGY   (United States)

^e INDIANA UNIVERSITY OF PENNSYLVANIA   (United States)

^f UNIVERSITY OF VERMONT   (United States)

^g RENSSELAER POLYTECHNIC INSTITUTE   (United States)

^h SYRACUSE UNIVERSITY   (United States)

ⁱ IEEE

^j CLARKSON UNIVERSITY   (United States)

^k NEW JERSEY INSTITUTE OF TECHNOLOGY   (United States)

more..

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; INTEGRATED CIRCUIT LAYOUT; INTEGRATED CIRCUIT TESTING; LOGIC DESIGN; MICROPROCESSOR CHIPS; OPTIMIZATION;

CHIP DENSITY; DESIGN FOR TESTABILITY; LOGIC SYNTHESIS;

APPLICATION SPECIFIC INTEGRATED CIRCUITS;

EID: 0030194664     PISSN: 00188646     EISSN: None     Source Type: Journal    
DOI: 10.1147/rd.404.0387     Document Type: Article

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