A Compile-Time Scheduling Heuristic for Interconnection-Constrained Heterogeneous Processor Architectures

IEEE Transactions on Parallel and Distributed Systems

Volumn 4, Issue 2, 1993, Pages 175-187

  Sih, Gilbert C ^a   Lee, Edward A ^b  

^a QUALCOMM INC   (United States)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

Compile time scheduling dynamic level hetero geneous processors interconnection constraints interprocessor communication parallel processing

Indexed keywords

COMPUTER ARCHITECTURE; PARALLEL PROCESSING SYSTEMS; SCHEDULING;

COMPILE-TIME SCHEDULING; INTERPROCESS COMMUNICATION;

PROGRAM COMPILERS;

EID: 0027542932     PISSN: 10459219     EISSN: None     Source Type: Journal    
DOI: 10.1109/71.207593     Document Type: Article

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