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Volumn 22, Issue 1, 1999, Pages 9-20

Clustering approach to explore grain-sizes in the definition of processing elements in dataflow architectures

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; ANALOG TO DIGITAL CONVERSION; COMPUTER ARCHITECTURE; DATA FLOW ANALYSIS;

EID: 0032671734     PISSN: 09225773     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1008113601237     Document Type: Article
Times cited : (2)

References (25)
  • 9
    • 0003212223 scopus 로고    scopus 로고
    • An approach for quantitative analysis of application-specific dataflow architectures
    • July 14-16
    • B. Kienhuis, E. Deprettere, K. Vissers, and P. van der Wolf, "An approach for quantitative analysis of application-specific dataflow architectures," Proc. ASAP '97, July 14-16, 1997.
    • (1997) Proc. ASAP '97
    • Kienhuis, B.1    Deprettere, E.2    Vissers, K.3    Van Der Wolf, P.4
  • 10
    • 0030686012 scopus 로고    scopus 로고
    • Prophid, a data-driven multi-processor architecture for high-performance DSP
    • March 17-20
    • J.A.J. Leijten, J.L. van Meerbergen, A.H. Timmer, and J.A.G. Jess, "Prophid, a data-driven multi-processor architecture for high-performance DSP," Proc. ED&TC, March 17-20 1997.
    • (1997) Proc. ED&TC
    • Leijten, J.A.J.1    Van Meerbergen, J.L.2    Timmer, A.H.3    Jess, J.A.G.4
  • 12
    • 0030717812 scopus 로고    scopus 로고
    • Synthesis of application specific programmable processors
    • K. Kim, R. Karri, and M. Potkonja, "Synthesis of application specific programmable processors," Proc. DAC 97, 1997.
    • (1997) Proc. DAC 97
    • Kim, K.1    Karri, R.2    Potkonja, M.3
  • 14
    • 0026174923 scopus 로고
    • Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications
    • June
    • S. Note, W. Geurts, F. Catthoor, and H. De Man, "Cathedral-III: Architecture-driven high-level synthesis for high throughput DSP applications," Proc. 28th DAC, pp. 597-602, June 1991.
    • (1991) Proc. 28th DAC , pp. 597-602
    • Note, S.1    Geurts, W.2    Catthoor, F.3    De Man, H.4
  • 16
    • 0030206111 scopus 로고    scopus 로고
    • Low-power architectural synthesis and the impact of exploiting locality
    • R. Mehra, L.M. Guerra, and J.M. Rabaey, "Low-power architectural synthesis and the impact of exploiting locality," Journal of VLSI Signal Processing, Vol. 13, pp. 239-258, 1996.
    • (1996) Journal of VLSI Signal Processing , vol.13 , pp. 239-258
    • Mehra, R.1    Guerra, L.M.2    Rabaey, J.M.3
  • 17
    • 0029734630 scopus 로고    scopus 로고
    • Recursive bipartitioning of signal flow graphs for programmable video signal processors
    • E.H.L. Aarts, G. Essink, and E.A. de Kock, "Recursive bipartitioning of signal flow graphs for programmable video signal processors," Proc. ED&TC96, pp. 460-466, 1996.
    • (1996) Proc. ED&TC96 , pp. 460-466
    • Aarts, E.H.L.1    Essink, G.2    De Kock, E.A.3
  • 18
    • 0344821919 scopus 로고
    • A variable-depth search algorithm for the recursive bipartitioning of signal flow graphs
    • E.A. de Kock, E.H.L. Aarts, G. Essink, R.E.J. Jansen, and J.H.M. Korst, "A variable-depth search algorithm for the recursive bipartitioning of signal flow graphs," OR Spektrum, Vol. 17, pp. 159-172, 1995.
    • (1995) OR Spektrum , vol.17 , pp. 159-172
    • De Kock, E.A.1    Aarts, E.H.L.2    Essink, G.3    Jansen, R.E.J.4    Korst, J.H.M.5
  • 24
    • 84990479742 scopus 로고
    • An efficient heuristic procedure for partitioning graphs
    • B.W. Kernighan and S. Lin, "An efficient heuristic procedure for partitioning graphs," Bell System Technical Journal, Vol. 49, pp. 291-307, 1970.
    • (1970) Bell System Technical Journal , vol.49 , pp. 291-307
    • Kernighan, B.W.1    Lin, S.2
  • 25
    • 85027124029 scopus 로고
    • Master's thesis, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology
    • J.W. Babb, "Virtual wires: Overcoming pin limitations in FPGA-based logic emulation," Master's thesis, Department of Electrical Engineering and Computer Science, Massachusetts Institute of Technology, 1993.
    • (1993) Virtual Wires: Overcoming Pin Limitations in FPGA-based Logic Emulation
    • Babb, J.W.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.