Consideration of performance limitation of sub-100-nm double-gate silicon-on-insulator (SOI) metal-oxide-semiconductor field-effect transistors (MOSFETs)

Japanese Journal of Applied Physics, Part 2: Letters

Volumn 41, Issue 10 A, 2002, Pages

  Yanagi, Shin Ichiro ^a   Omura, Yasuhisa ^a  

^a KANSAI UNIVERSITY   (Japan)

Author keywords

Drivability; Electron velocity; Intrinsic channel double gate; Silicon on insulator; Single gate

Indexed keywords

COMPUTER SIMULATION; ELECTRIC FIELD EFFECTS; ELECTRON TUNNELING; HYDRODYNAMICS; SILICON ON INSULATOR TECHNOLOGY;

TUNNELING EFFECT;

MOSFET DEVICES;

EID: 0036814284     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/jjap.41.l1096     Document Type: Article

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