Impact of polymetal gate etch post-cleaning on data retention time in sub-micron DRAM cells

Japanese Journal of Applied Physics, Part 1: Regular Papers and Short Notes and Review Papers

Volumn 41, Issue 4 B, 2002, Pages 2385-2389

  Kim, Nam Sung ^a   Kim, Il Gweon ^a   Choy, Jun Ho ^a   Park, Joo Seog ^a  

^a Hynix Semiconductor Inc   (South Korea)

Author keywords

DRAM data retention time; GIDL; Interface quality; Interface trap density; Polymetal gate etch post cleaning; Trace impurities; Unwanted residues (byproducts)

Indexed keywords

ETCHING; GATES (TRANSISTOR);

DRAM DATA RETENTION TIME; INTERFACE QUALITY; POLYMETAL GATE ETCH POST-CLEANING; TRACE IMPURITIES;

DYNAMIC RANDOM ACCESS STORAGE;

EID: 0011449495     PISSN: 00214922     EISSN: None     Source Type: Journal    
DOI: 10.1143/JJAP.41.2385     Document Type: Article

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