Optimal Configuring of Multiple Scan Chains

IEEE Transactions on Computers

Volumn 42, Issue 9, 1993, Pages 1121-1131

  Narayanan, Sridhar ^a   Gupta, Rajesh ^b  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

^b IBM   (United States)

Author keywords

Dynamic programming; equal length chains; full; multiple scan chains; optimal chain configurations; partial scan; polynomial time complexity; scan; test application time

Indexed keywords

CIRCUIT THEORY; COMPUTER CIRCUITS; DIGITAL CIRCUITS; DYNAMIC PROGRAMMING; ELECTRIC NETWORK TOPOLOGY; FLIP FLOP CIRCUITS; LOGIC CIRCUITS; LOGIC DESIGN; NETWORKS (CIRCUITS); SWITCHING THEORY;

EQUAL LENGTH CHAINS; MULTIPLE SCAN CHAINS; OPTIMAL CHAIN CONFIGURATIONS; POLYNOMIAL TIME COMPLEXITY; SERIAL SCAN DESIGNS;

ELECTRIC NETWORK ANALYSIS;

EID: 0027663733     PISSN: 00189340     EISSN: None     Source Type: Journal    
DOI: 10.1109/12.241600     Document Type: Article

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