Design of VLSI CMOS circuits under thermal constraint

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 49, Issue 8, 2002, Pages 589-593

  Daasch, W Robert ^a   Lim, Chee How ^a,b   Cai, George ^b  

^a Department of Electrical and Computer Engineering   (United States)

^b INTEL CORPORATION   (United States)

Author keywords

Energy delay product (EDP); Power performance tradeoff; Thermal control; Very large scale integration (VLSI) CMOS design

Indexed keywords

ALGORITHMS; ELECTRIC POTENTIAL; ENERGY UTILIZATION; FREQUENCIES; RELIABILITY; THERMAL EFFECTS; VLSI CIRCUITS;

DYNAMIC CLOCK THROTTLING (DCT);

CMOS INTEGRATED CIRCUITS;

EID: 0036704757     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/TCSII.2002.806247     Document Type: Article

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