New optimization strategy for CMOS device process in the era of 0.2 μm and beyond for MPU's and ASIC's

Proceedings of the Custom Integrated Circuits Conference

Volumn , Issue , 1998, Pages 155-158

  Mori, Kazutaka ^a   Kikushima, Ken'ichi ^a   Ootsuka, Fumio ^a   Mitani, Shin'ichiro ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ELECTRIC WIRING; HEAT RESISTANCE; INTEGRATED CIRCUIT MANUFACTURE; WIRE;

THERMAL RUNAWAY; WIRING CHANNEL DENSITY;

CMOS INTEGRATED CIRCUITS;

EID: 0031617881     PISSN: 08865930     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (3)