An improved bang-bang phase detector for clock and data recovery applications

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 1, Issue , 2001, Pages 715-718

  Ramezani, Mehrdad ^a   Salama, C Alzdre T ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

BANG-BANG PHASE DETECTORS; CLOCK AND DATA RECOVERY; DESIGN SENSITIVITY; DIFFERENTIAL TOPOLOGY; FULLY INTEGRATED; JITTER PERFORMANCE; POWER-SUPPLY NOISE; TOTAL POWER DISSIPATION;

CLOCK AND DATA RECOVERY CIRCUITS (CDR CIRCUITS); CLOCKS; CMOS INTEGRATED CIRCUITS; JITTER; SIGNAL DETECTION; ATOMIC CLOCKS; FREQUENCY CONVERTERS; PHASE SHIFT; TOPOLOGY; VARIABLE FREQUENCY OSCILLATORS;

LOW POWER ELECTRONICS; BANG BANG CONTROL SYSTEMS;

DATA RECOVERY; PHASE DETECTORS;

EID: 0034996297     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.921956     Document Type: Conference Paper

References (6)

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3. K. Nakamura, M. Fukaishi, H. Abiko, A. Matsumoto and M. Yotsuyanagi", A 6Gbps CMOS Phase Detecting DEMUX Module Using Half-Frequency Clock" Digest of Symposium on VLSI Circuits. pp. 196-197. 1998
4. M. Rau. T. Oberst. R. Lares, A. Rothermel, R. Schweer, and N. Menoux", Clock/Data Recovery PLL Using Half-Frequency Clock ". IEEE Journal of Solid-State Circuits, pp. 1156-1160. 1997.
5. D. G. Messerschmitt. "Frequency Detectors for PLL Acquisition in Timing and Carrier Recovery", IEEE Transaction on Communications. Vol. 27, pp. 1288-1295, 1979.
6. B. Razavi. "' Monolithic Phase-Locked Loops and Clock Recovery Circuits", IEEE Press. New York. 1996.