Design of low jitter PLL for clock generator with supply noise insensitive VCO

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 1998, Pages 233-236

  Lee, Chang Hyeon ^a   Cornish, Jack ^a   McClellan, Kelly ^a   Choma Jr , John ^a  

^a UNIVERSITY OF SOUTHERN CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; SPURIOUS SIGNAL NOISE; TIMING CIRCUITS; VARIABLE FREQUENCY OSCILLATORS;

BANDGAP REGULATORS; PHASE NOISE; TIMING JITTER;

PHASE LOCKED LOOPS;

EID: 0031622717     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)