Linearly graded doping drift region: A novel lateral voltage-sustaining layer used for improvement of RESURF LDMOS transistor performances

Semiconductor Science and Technology

Volumn 17, Issue 7, 2002, Pages 721-728

  He, Jin ^a,b   Xi, Xuemei ^b   Chan, Mansun ^b   Hu, Chenming ^b   Li, Yingxue ^a   Xing, Zhang ^a   Huang, Ru ^a  

^a PEKING UNIVERSITY   (China)

^b UNIVERSITY OF CALIFORNIA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTER SIMULATION; ELECTRIC BREAKDOWN; ELECTRIC FIELD EFFECTS; ELECTRIC RESISTANCE; MOSFET DEVICES; SIMULATORS;

LATERAL DOUBLE DIFFUSED MOS TRANSISTOR; LATERAL VOLTAGE SUSTAINED LAYER; LINEARLY GRADED DOPING DRIFT REGION STRUCTURE; SEMICONDUCTOR DEVICE SIMULATOR; SOFTWARE PACKAGE MEDICI;

SEMICONDUCTOR DOPING;

EID: 0036641984     PISSN: 02681242     EISSN: None     Source Type: Journal    
DOI: 10.1088/0268-1242/17/7/315     Document Type: Article

References (20)

1. High voltage thin layer devices
2. Effects of drift region parameters on the static properties of power LDMOST
3. High-voltage multiple-resistivity drift-region LDMOS
4. Modeling and process implementation of implanted RESURF type devices
5. Breakdown voltage enhancement for device on thin silicon layer/silicon dioxide film
6. Optimization of the drift region of power MOSFET's with lateral structure and deep junctions
7. Optimization of RESURF LDMOS transistors: An analytical approach
8. Lateral high-voltage devices using an optimal variation lateral doping
9. Multiple-zone single-mask junction termination extension - A high-yield near-ideal breakdown voltage technology
10. Variation of lateral doping - A novel concept to avoid high voltage breakdown of planar junctions
11. Realization of a high-voltage planar junction terminations for power devices
12. Realization of high breakdown voltage (>700 V) in thin SOI devices
13. Analytical model for the electrical field distribution in SOI RESURF and TMBS structures
14. Dependence of breakdown voltage on drift length and buried oxide thickness in SOI RESURF LDMOS transistor
15. Implementation of linear doping profile for high-voltage thin-film SOI devices
16. Numerical modeling of linear doping profiles for high-voltage thin-film SOI devices
17. Calculation of avalanche breakdown voltage of the silicon p-n junctions
18. Deep sub-micrometer double-gate fully-depleted SOI PMOS devices: A concise short-channel effect threshold voltage model using a quasi-2D approach
19. Comparison and extension of recent surface potential models for fully depleted short-channel SOI MOSFET's
20. Effect of junction curvature on breakdown voltage of abrupt cylindrical and spherical junctions