Analysis of boron penetration and gate depletion using dual-gate PMOSFETs for high performance G-bit DRAM design

IEICE Transactions on Electronics

Volumn E85-C, Issue 5, 2002, Pages 1138-1145

  Takaura, Norikatsu ^a   Nagai, Ryo ^a   Asakura, Hisao ^a   Yamada, Satoru ^a   Kimura, Shinichiro ^a  

^a HITACHI LTD   (Japan)

Author keywords

Boron penetration; Dual gate PMOS FETs; G bit DRAM; Gate depletion

Indexed keywords

ANNEALING; CAPACITANCE MEASUREMENT; CURRENT VOLTAGE CHARACTERISTICS; DYNAMIC RANDOM ACCESS STORAGE; FABRICATION; GATES (TRANSISTOR); NUMERICAL ANALYSIS; POISSON EQUATION; SECONDARY ION MASS SPECTROMETRY; SEMICONDUCTING BORON; SUBSTRATES; THRESHOLD VOLTAGE;

FLUCTUATION; GATE DEPLETION; SHALLOW TRENCH ISOLATION; VOLTAGE SHIFT;

MOSFET DEVICES;

EID: 0036579505     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (12)

1. + polycrystalline silicon and boron penetration
2. Modeling the polysilicon depletion effect and its impact on submicrometer CMOS circuit performance
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5. Effects of gate depletion and boron penetration on matching of deep submicron CMOS transistors
6. x/dual-poly Si stacked-gate by using wet hydrogen oxidation in 0.14-mm CMOS devices
7. The effects of boron penetration on p/sup +/polysilicon gated PMOS devices