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Volumn , Issue , 1998, Pages 469-472

Ftd: An exact frequency to time domain conversion for reduced order RLC interconnect models

Author keywords

[No Author keywords available]

Indexed keywords

CONVOLUTION; FREQUENCY DOMAIN ANALYSIS; PIECEWISE LINEAR TECHNIQUES; STATE SPACE METHODS; ALGORITHMS; COMPUTER SIMULATION; MATHEMATICAL MODELS; RECURSIVE FUNCTIONS; TIME DOMAIN ANALYSIS; WAVEFORM ANALYSIS;

EID: 0031619493     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (8)

References (7)
  • 2
    • 0028517129 scopus 로고
    • Time-domain macro- models for VLSI interconnect analysis
    • Oct
    • S.-Y.Kim, N. Gopal and L. T. Pillage, "Time-Domain Macro- models for VLSI Interconnect Analysis", IEEE Trans, on CAD, vol. 13, No. 10, Oct. 1994.
    • (1994) IEEE Trans, on CAD , vol.13 , Issue.10
    • Kim, S.-Y.1    Gopal, N.2    Pillage, L.T.3
  • 3
    • 85053162732 scopus 로고
    • Efficient simulation of lossy and dispersive transmission lines
    • T.V. Nguyen, "Efficient Simulation of Lossy and Dispersive Transmission Lines", IEEE/ACM Proc. DAC, 1994.
    • (1994) IEEE/ACM Proc. DAC
    • Nguyen, T.V.1
  • 4
    • 0025414182 scopus 로고
    • Asymptotic waveform evaluation for timing analysis
    • Apr
    • L.T. Pillage and R. A. Rohrer, "Asymptotic Waveform Evaluation for Timing Analysis", IEEE Trans, on CAD, vol. 9, no. 4, Apr. 1990.
    • (1990) IEEE Trans, on CAD , vol.9 , Issue.4
    • Pillage, L.T.1    Rohrer, R.A.2
  • 6
    • 0031622742 scopus 로고    scopus 로고
    • TETA: Transistor-level engine for timing analysis
    • Jun
    • F.Dartu and L.T. Pileggi, "TETA: Transistor-Level Engine for Timing Analysis", IEEE/ACM Proc. DAC, Jun. 1998.
    • (1998) IEEE/ACM Proc. DAC
    • Dartu, F.1    Pileggi, L.T.2
  • 7
    • 85053151681 scopus 로고    scopus 로고
    • Ftd: A frequency to time domain conversion algorithm for interconnect simulation
    • submitted to
    • Y.Liu, L.T. Pileggi and A.J. Strojwas, "ftd: A Frequency to Time Domain Conversion Algorithm for Interconnect Simulation", submitted to IEEE Tran. CAD.
    • IEEE Tran. CAD
    • Liu, Y.1    Pileggi, L.T.2    Strojwas, A.J.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.