An efficient partial order reduction algorithm with an alternative proviso implementation

Formal Methods in System Design

Volumn 20, Issue 3, 2002, Pages 231-247

  Nalumasu, Ratan ^a   Gopalakrishnan, Ganesh ^a  

^a Department of Electrical and Computer Engineering   (United States)

Author keywords

Concurrent protocol verification; Explicit enumeration; In stack checking; On the fly model checking; Partial order reductions; Proviso; Temporal logic

Indexed keywords

ALGORITHMS; CACHE MEMORY; MATHEMATICAL MODELS; NETWORK PROTOCOLS; STATE SPACE METHODS;

PARTIAL ORDER REDUCTIONS;

SYSTEMS ANALYSIS;

EID: 0036569880     PISSN: 09259856     EISSN: None     Source Type: Journal    
DOI: 10.1023/A:1014728912264     Document Type: Article

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