Construction of a cost-effective failure analysis service network - Microelectronic failure analysis service in Japan

Microelectronics Reliability

Volumn 42, Issue 4-5, 2002, Pages 511-521

  Nakajima, S ^a   Nakamura, S ^a   Kuji, K ^a   Ueki, T ^a   Ajioka, T ^a   Sakai, T ^a,b  

^a NTT CORPORATION   (Japan)

^b TOKYO INSTITUTE OF TECHNOLOGY   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

FAILURE ANALYSIS SERVICE NETWORKS;

COMPUTER SOFTWARE; FAILURE ANALYSIS; GATES (TRANSISTOR); LSI CIRCUITS; SEMICONDUCTOR DEVICE TESTING; SURFACE TESTING;

MICROELECTRONICS;

EID: 0036540842     PISSN: 00262714     EISSN: None     Source Type: Journal    
DOI: 10.1016/S0026-2714(02)00043-4     Document Type: Article

References (5)

1. Failure analysis from the backside of a die
2. Observation of the internal waveform in high-seed high-density LSIs using an EOS prober
3. Scanning SQUID microscopy for current imaging
4. Quantification of scanning capacitance microscopy measurement for 2D dopant profiling
5. EB-testing-pad method and its evaluation by actual devices