A DFT technique for low frequency delay fault testing in high performance digital circuits

IEEE International Test Conference (TC)

Volumn , Issue , 2002, Pages 1130-1139

  Chatterjee, Bhaskar ^a   Sachdev, Manoj ^a   Keshavarzi, Ali ^b  

^a Dept of Electrical and Comp Eng ^*  (Canada)

^b INTEL CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ADDERS; CMOS INTEGRATED CIRCUITS; DELAY CIRCUITS; DIGITAL INTEGRATED CIRCUITS; ELECTRIC FREQUENCY MEASUREMENT; ELECTRIC POWER MEASUREMENT; FAILURE ANALYSIS; MICROELECTRONIC PROCESSING;

DELAY FAULT TESTING; MINIMAL POWER PENALTY; TEST MODE CLOCK FREQUENCY;

DESIGN FOR TESTABILITY;

EID: 0036443157     PISSN: 10893539     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

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