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Volumn 2000-January, Issue , 2000, Pages 181-188

On effective IDDQ testing of low voltage CMOS circuits using leakage control techniques

Author keywords

[No Author keywords available]

Indexed keywords

VECTOR CONTROL (ELECTRIC MACHINERY);

EID: 0011797812     PISSN: 19483287     EISSN: 19483295     Source Type: Conference Proceeding    
DOI: 10.1109/ISQED.2000.838872     Document Type: Conference Paper
Times cited : (4)

References (24)
  • 1
    • 0029698339 scopus 로고    scopus 로고
    • A novel builtin current sensor for I DDQ testing of deep submicron CMOS ICs
    • S. Athan, D. Landis, and S. Al-Arian, "A Novel Builtin Current Sensor for I DDQ Testing of Deep Submicron CMOS ICs", IEEE VLSI Test Symposium, 1996, pp. 118-123.
    • (1996) IEEE VLSI Test Symposium , pp. 118-123
    • Athan, S.1    Landis, D.2    Al-Arian, S.3
  • 6
    • 0029292445 scopus 로고
    • CMOS scaling for high performance and low power - The next ten years
    • B. Davari, R. Dennard and G. Shahidi, "CMOS Scaling for High Performance and Low Power - The Next Ten Years", Proceedings of the IEEE, Vol. 83, No. 4, pp. 595, 1995.
    • (1995) Proceedings of the IEEE , vol.83 , Issue.4 , pp. 595
    • Davari, B.1    Dennard, R.2    Shahidi, G.3
  • 9
    • 0002746446 scopus 로고
    • Electronics Research Laboratory, University of California, Berkeley
    • M. C. Jeng, "Design and Modeling of Deep-Submicrometer MOSFETS", Electronics Research Laboratory, Rep. No. ERL-M90/90, University of California, Berkeley, 1990.
    • (1990) Design and Modeling of Deep-submicrometer MOSFETS
    • Jeng, M.C.1
  • 13
    • 0029713581 scopus 로고    scopus 로고
    • Genetic-algorithm-based test generation for current testing of bridging faults in CMOS VLSI circuits
    • T. Lee, I. Hajj, E. Rudnick, and J. Patel, "Genetic-Algorithm-Based Test Generation for Current Testing of Bridging Faults in CMOS VLSI Circuits", 14 th VLSI Test Symposium, 1996, pp. 456-462.
    • (1996) 14 Th VLSI Test Symposium , pp. 456-462
    • Lee, T.1    Hajj, I.2    Rudnick, E.3    Patel, J.4
  • 14
    • 0002152672 scopus 로고
    • Enhancement of resolution in supply current based testing for large ICs
    • Y. K. Malaiya, et. al., "Enhancement of Resolution in Supply Current Based Testing for Large ICs", IEEE VLSI Test Symposium, pp. 291-296, 1991.
    • (1991) IEEE VLSI Test Symposium , pp. 291-296
    • Malaiya, Y.K.1
  • 17
    • 0030120870 scopus 로고    scopus 로고
    • Ddq testing for signal and bias paths in CMOS ICs for defect diagnosis
    • Ddq Testing for Signal and Bias Paths in CMOS ICs for Defect Diagnosis", Journal of Electronic Testing: Theory and Application, Vol. 8, pp. 203-214, 1996.
    • (1996) Journal of Electronic Testing: Theory and Application , vol.8 , pp. 203-214
    • Sachdev, M.1
  • 23
    • 0033100297 scopus 로고    scopus 로고
    • Design and optimization of dual threshold circuits for low voltage low power applications
    • March
    • L. Wei, Z. Chen, M. John, K. Roy, Y. Ye, and V. De, "Design and Optimization of Dual Threshold Circuits for Low Voltage Low Power Applications", IEEE Transactions on VLSI Systems, March 1999.
    • (1999) IEEE Transactions on VLSI Systems
    • Wei, L.1    Chen, Z.2    John, M.3    Roy, K.4    Ye, Y.5    De, V.6
  • 24
    • 84950127452 scopus 로고    scopus 로고
    • Standby leakage reduction in high-performance circuits using transistor stack effects
    • Y. Ye, S. Borkar and V. De, "Standby Leakage Reduction in High-Performance Circuits Using Transistor Stack Effects", VLSI Symposium, 1998.
    • (1998) VLSI Symposium
    • Ye, Y.1    Borkar, S.2    De, V.3


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.