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Volumn 4746 I, Issue , 2002, Pages 551-556

ESD reliability issues in RF CMOS circuits

Author keywords

[No Author keywords available]

Indexed keywords

AMPLIFIERS (ELECTRONIC); ELECTRIC DISCHARGES; ELECTRIC EQUIPMENT PROTECTION; ELECTRIC LOADS; ELECTROSTATICS; INTEGRATED CIRCUIT LAYOUT; RELIABILITY;

EID: 0036407891     PISSN: 0277786X     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper
Times cited : (1)

References (14)
  • 2
    • 0032308764 scopus 로고    scopus 로고
    • ESD related process effects in mixed-voltage sub-0.5um technologies
    • V. Gupta, et al., "ESD related process effects in Mixed-voltage sub-0.5um technologies", Proc. EOS/ESD Symp., pp. 161-169, 1998.
    • (1998) Proc. EOS/ESD Symp. , pp. 161-169
    • Gupta, V.1
  • 3
    • 0031377817 scopus 로고    scopus 로고
    • Study of the ESD behavior of different clamp configurations in a 0.35um CMOS technology
    • C. Richier, et al., "Study of the ESD behavior of different clamp configurations in a 0.35um CMOS technology", Proc. EOS/ESD Symp. pp.240-245, 1997.
    • (1997) Proc. EOS/ESD Symp. , pp. 240-245
    • Richier, C.1
  • 4
    • 0011133926 scopus 로고    scopus 로고
    • ESD protection methodology for deep sub-micron CMOS
    • Bock, K, et al., ESD protection methodology for deep sub-micron CMOS,' ", Proc. ESREF 98, pp. 97-100, 1998.
    • (1998) Proc. ESREF , vol.98 , pp. 97-100
    • Bock, K.1
  • 7
    • 0003765041 scopus 로고    scopus 로고
    • ESD characterization of IC's - Transmission line pulser
    • ind. Eng. Thesis
    • S. Servaes and B. Keppens, "ESD characterization of IC's - Transmission line pulser", ind. Eng. Thesis, 1996.
    • (1996)
    • Servaes, S.1    Keppens, B.2
  • 8
    • 33645137480 scopus 로고    scopus 로고
    • Contributions to standardization of transmission line pulse testing methodology
    • Keppens B. et al., 'Contributions to Standardization of transmission line pulse testing methodology', Proc. EOS/ESD symp. 2001, pp.461-467
    • Proc. EOS/ESD Symp. 2001 , pp. 461-467
    • Keppens, B.1
  • 9
    • 0033279350 scopus 로고    scopus 로고
    • Influence of gate length on ESD performance for deep sub micron CMOS technology
    • K. Bock, et al., "Influence of gate length on ESD performance for deep sub micron CMOS technology", Proc. EOS/ESD Symp., pp. 95-104, 1999.
    • (1999) Proc. EOS/ESD Symp. , pp. 95-104
    • Bock, K.1
  • 10
    • 0002841217 scopus 로고    scopus 로고
    • Investigation on different ESD protection strategies devoted to 3.3V RF applications in a 0.18 CMOS process
    • C. Richier et al., 'Investigation on Different ESD protection strategies devoted to 3.3V RF applications in a 0.18 CMOS process' Proc. EOS/ESD Symp. 2000, pp.251-259
    • Proc. EOS/ESD Symp. 2000 , pp. 251-259
    • Richier, C.1
  • 12
    • 0034249970 scopus 로고    scopus 로고
    • Distributed ESD protection for high speed integrated circuits
    • B. Kleveland, et al., "Distributed ESD protection for high speed integrated circuits", IEEE Electron. Dev. Lett., 21(8), pp. 390-392, 2000.
    • (2000) IEEE Electron. Dev. Lett. , vol.21 , Issue.8 , pp. 390-392
    • Kleveland, B.1
  • 13
    • 0011104456 scopus 로고    scopus 로고
    • Analysis and optimization of distributed ESD protection circuits for high speed mixed signal and RF applications
    • Ito C. et al., 'Analysis and optimization of distributed ESD protection circuits for high speed mixed signal and RF applications' Proc. EOS/ESD Symp. 2001, pp.355-363.
    • Proc. EOS/ESD Symp. 2001 , pp. 355-363
    • Ito, C.1
  • 14
    • 0035391528 scopus 로고    scopus 로고
    • A sub-1-db NF +/-2.3kV ESD protected 900MHz CMOS LNA
    • G. Gramegna, et al., "A sub-1-db NF +/-2.3kV ESD protected 900MHz CMOS LNA", IEEE Jl. Solid State Circuits, 36(7), pp. 1010-1017, 2001.
    • (2001) IEEE Jl. Solid State Circuits , vol.36 , Issue.7 , pp. 1010-1017
    • Gramegna, G.1


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.