Timing optimization of mixed static and domino logic

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 6, Issue , 1998, Pages 266-269

  Zhao, Min ^a   Sapatnekar, Sachin S ^a  

^a UNIVERSITY OF MINNESOTA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; OPTIMIZATION; TIMING CIRCUITS; TRANSISTORS;

DOMINO LOGIC;

SEQUENTIAL CIRCUITS;

EID: 0031635606     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)