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Volumn , Issue , 2002, Pages 40-49

Efficient architectures for implementing montgomery modular multiplication and RSA modular exponentiation on reconfigurable logic

Author keywords

Encryption; Exponentiation; FPGA; Modular Multiplication; Montgomery; Public key; RSA

Indexed keywords

ALGORITHMS; LOGIC DESIGN; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; PUBLIC KEY CRYPTOGRAPHY; TIMING CIRCUITS;

EID: 0036385605     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/503048.503055     Document Type: Conference Paper
Times cited : (82)

References (14)
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    • Jeong, Y.-J.1    Burleson, W.P.2
  • 4
    • 0028482946 scopus 로고
    • A systolic, linear-array multiplier for a class of right-shift algorithms
    • Aug.
    • Peter Kornerup. "A Systolic, Linear-Array Multiplier for a Class of Right-Shift Algorithms". IEEE Transactions on Computers, 43(8):892-898, Aug. 1994.
    • (1994) IEEE Transactions on Computers , vol.43 , Issue.8 , pp. 892-898
    • Kornerup, P.1
  • 5
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    • Mar
    • C. D. Walter. "Systolic modular multiplication". IEEE Transactions on Computers, 42:376-378, Mar 1993.
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    • Walter, C.D.1
  • 6
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    • S. E. Eldridge and C. D. Walter. "Hardware implementation of Montgomery's modular multiplication algorithm". IEEE Transactions on Computers, 42:693-699, June 1993.
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    • Eldridge, S.E.1    Walter, C.D.2
  • 7
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    • Walter, C.D.1
  • 8
    • 0032049394 scopus 로고    scopus 로고
    • Optimised bit serial modular multiplier for implementation on field programmable gate arrays
    • April
    • W. P. Marnane. "Optimised bit serial modular multiplier for implementation on field programmable gate arrays". IEE Electronics Letters, 34(8):738-739, April 1998.
    • (1998) IEE Electronics Letters , vol.34 , Issue.8 , pp. 738-739
    • Marnane, W.P.1
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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.