Two implementation methods of a 1024-bit RSA cryptoprocessor based on modified Montgomery algorithm

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 650-653

  Kwon, Taek Won ^a   You, Chang Seok ^a   Heo, Won Seok ^a   Kang, Yong Kyu ^a   Choi, Jun Rim ^a  

^a Kyungpook National University   (South Korea)

Author keywords

[No Author keywords available]

Indexed keywords

BINARY METHOD; CRYPTO-PROCESSOR; HARDWARE RESOURCES; MODULAR MULTIPLICATION; MONTGOMERY ALGORITHM; PROPOSED ARCHITECTURES; RSA PROCESSORS; SPEED IMPROVEMENT;

ALGORITHMS; HARDWARE;

COMPUTER ARCHITECTURE;

EID: 84888068366     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922321     Document Type: Conference Paper

References (5)

1. R. L. Rivest, A. Shamir, and L. Adleman. "A method for obtaining digital signature and public-key cryptosystems," Comm. ACM. vol.21, pp. 120-126. 1978.
2. P. L. Montgomery. "Modular multiplication without trial division." Math. Computation, vol. 44, pp.519-521, 1985.
3. T. Blum and C. Paar, "Montgomery modular exponentiation on reconfigurable hardware," in Proc. 14th IEEE Symp. on Computer Arithmetic. 1999, pp. 70-77.
4. S. E. Eldridge and C. D. Walter. "Hardware implementation of Montgomery's modular multiplication algorithm." IEEE Trans. Comput. vol. 42. pp. 693-699, June 1993.
5. C. C. Yang. T. S. Chang, and C. W. Jen. "A new RSA cryptosystem hardware design based on Montgomery's algorithm," IEEE Trans. Circuits and Systems II: Analog and Digital Signal Processing, vol. 45. pp. 908-913, July 1998.