Optimised bit serial modular multiplier for implementation on field programmable gate arrays

Electronics Letters

Volumn 34, Issue 8, 1998, Pages 738-739

  Marnane, W P ^a  

^a UNIVERSITY COLLEGE CORK   (Ireland)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC GATES; MATHEMATICAL MODELS; OPTIMIZATION;

FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

MULTIPLYING CIRCUITS;

EID: 0032049394     PISSN: 00135194     EISSN: None     Source Type: Journal    
DOI: 10.1049/el:19980286     Document Type: Article

References (9)

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4. 'The programmable logic data book' (Xilinx Inc., San Jose, California, USA, 1995)
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7. REILLY, F.J.O., MARNANE, W.P., and MURPHY, P.J.: Optimising designs for hardware compilation to FPGAs'. Proc. 1997 IEEE Workshop on Signal processing systems, SiPS 97, 1997, pp. 522-531
8. MARNANE, W.P., JORDAN, C.J., and REILLY, F.J.O.: 'Compiling regular arrays onto FPGAs' in 'Lecture notes in computer science 975, Field-programmable logic and applications' (Springer-Verlag, 1995), pp. 178-187
9. KOC, C.K., ACAR, T., and KALISKI, B.S.: 'Analyzing and comparing Montgomery multiplication algorithms', IEEE Micro, 1996, pp. 26-33