A study of current multilevel interconnect technologies for 90 nm nodes and beyond

Fujitsu Scientific and Technical Journal

Volumn 38, Issue 1, 2002, Pages 13-21

  Ohba, Takayuki ^a  

^a FUJITSU LABORATORIES LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CAPACITANCE; INTERNET; LOGIC DEVICES; MULTIMEDIA SYSTEMS; TRANSISTORS;

MULTILEVEL INTERCONNECT TECHNOLOGIES;

LARGE SCALE SYSTEMS;

EID: 0036326331     PISSN: 00162523     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

References (11)

1. Interconnection from design prospective
2. A new era of system integration and packaging
3. Multilevel interconnect technologies in SoC and SiP for 100-nm node and beyond
4. GHz interconnect in ULSI
5. Planarized copper multilevel interconnections for ULSI applications
6. Material and process challenges in 100-nm interconnects module technology and beyond
7. Copper dual damascene interconnects with very low-k dielectrics targeting for 130 nm node
8. Dual damascene: A ULSI wiring technology
9. Selective and blanket electroless copper deposition for ultralarge scale integration
10. Room temperature evolution of microstructure and resistivity in electroplated copper films
11. Current status and issues for Cu interconnect technology