Analytical model for switching transitions of submicron CMOS logics

IEEE Journal of Solid-State Circuits

Volumn 32, Issue 6, 1997, Pages 880-889

  Park, Heung Joon ^a,b,c,d,e   Soma, Mani ^{a,b,f,g,h,i,j}  

^a IEEE   (United States)

^b University of Washington   (United States)

^c Sogang University   (South Korea)

^d Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

^e Goldstar Electron Co   (United States)

^f CALIFORNIA STATE UNIVERSITY   (United States)

^g STANFORD UNIVERSITY   (United States)

^h GE GLOBAL RESEARCH   (United States)

ⁱ NSF Ctr Des Analog Digit I

^j UNIVERSITY OF WASHINGTON   (United States)

more..

Author keywords

Analytical model; Convolution; Delay; Linear system; Submicron CMOS logic; Switching transition

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; ELECTRIC INVERTERS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MOS DEVICES; SWITCHING;

CONVOLUTION THEORY; LINEAR SYSTEM; SWITCHING TRANSITION;

LOGIC CIRCUITS;

EID: 0031168374     PISSN: 00189200     EISSN: None     Source Type: Journal    
DOI: 10.1109/4.585290     Document Type: Article

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