A parametric solder joint reliability model for wafer level-chip scale package

Proceedings - Electronic Components and Technology Conference

Volumn , Issue , 2002, Pages 1323-1328

  Pitarresi, J ^a   Chaparala, S ^a   Sammakia, B ^a   Nguyen, L ^b   Patwardhan, V ^b   Zhang, L ^b   Kelkar, N ^b  

^a State University of New York   (United States)

^b NATIONAL SEMICONDUCTOR CORPORATION   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

EUTECTICS; FATIGUE OF MATERIALS; FLIP CHIP DEVICES; MATHEMATICAL MODELS; PERSONAL DIGITAL ASSISTANTS; RELIABILITY THEORY; SHOCK TESTING; SOLDERED JOINTS; SURFACE MOUNT TECHNOLOGY; THERMAL CYCLING; THERMAL STRESS;

THERMO-MECHANICAL STRESSES;

CHIP SCALE PACKAGES;

EID: 0036294561     PISSN: 05695503     EISSN: None     Source Type: Journal    
DOI: 10.1109/ECTC.2002.1008277     Document Type: Article

References (10)

1. Wafer level packaging has arrived
2. Micro SMD - A wafer level chip scale package
3. Wafer level chip scale packaging - Solder joint reliability
4. Constitutive equations for hot-working of metals
5. Reliability of plastic ball grid array assembly
6. Solder joint fatigue life model
7. Effect of simulation methodology on solder joint crack growth correlation
8. Sample preparation for moiré interferometry