Design of low-voltage CMOS pipelined ADC's using 1 pico-Joule of energy per conversion

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 1, Issue , 2002, Pages

  Vaz, B ^a   Paulino, N ^a   Goes, J ^a   Costa, R ^a   Tavares, R ^a   Steiger Garcao A ^a  

^a UNINOVA   (Portugal)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; ELECTRIC POTENTIAL; ENERGY DISSIPATION; GENETIC ALGORITHMS; INTEGRATED CIRCUIT LAYOUT; OPERATIONAL AMPLIFIERS; OPTIMIZATION; PIPELINE PROCESSING SYSTEMS; THERMAL NOISE;

CLOCK BOOSTING TECHNIQUE; DIFFERENTIAL NONLINEARITY; DYNAMIC LINK LIBRARY; POWER EFFICIENCY; SWITCHED OPERATIONAL AMPLIFIER;

ANALOG TO DIGITAL CONVERSION;

EID: 0036292221     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (12)

1. A 10-b 15-MHz CMOS recycling two-step A/D converter
2. Optimizing the stage resolution in pipelined, multistage, analog-to-digital converters for video-rate applications
3. Systematic design for optimization of high-speed pipelined A/D converters using self-calibration
4. A power optimized 13-b 5 Msamples/s pipelined analog-to-digital converter in 1.2 μm CMOS
5. A 15b 5Msample/s low-spurious CMOS ADC
6. A 14-bit 10 MHz calibration-free CMOS pipelined A/D converter
7. Analog technology of all varieties dominate ISSCC
8. 1.0-volt, 9-bit pipelined CMOS ADC
9. A 1.5-V, 10-bit, 14.3-MS/s CMOS pipeline analog-to-digital converter
10. Design methodology for optimisation of analogue building-blocks using genetic algorithms
11. A general-purpose kernel based on genetic algorithms for optimization of complex analog circuits