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Volumn 1, Issue , 2002, Pages
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Design of low-voltage CMOS pipelined ADC's using 1 pico-Joule of energy per conversion
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Author keywords
[No Author keywords available]
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Indexed keywords
CMOS INTEGRATED CIRCUITS;
ELECTRIC POTENTIAL;
ENERGY DISSIPATION;
GENETIC ALGORITHMS;
INTEGRATED CIRCUIT LAYOUT;
OPERATIONAL AMPLIFIERS;
OPTIMIZATION;
PIPELINE PROCESSING SYSTEMS;
THERMAL NOISE;
CLOCK BOOSTING TECHNIQUE;
DIFFERENTIAL NONLINEARITY;
DYNAMIC LINK LIBRARY;
POWER EFFICIENCY;
SWITCHED OPERATIONAL AMPLIFIER;
ANALOG TO DIGITAL CONVERSION;
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EID: 0036292221
PISSN: 02714310
EISSN: None
Source Type: Conference Proceeding
DOI: None Document Type: Conference Paper |
Times cited : (11)
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References (12)
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