Transient-induced latchup testing of CMOS integrated circuits

Electrical Overstress/Electrostatic Discharge Symposium Proceedings

Volumn , Issue , 1995, Pages 194-198

  Weiss, Gary H ^a   Young, Drew E ^a  

^a LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

BIPOLAR TRANSISTORS; COMPUTER SIMULATION; ELECTRIC CURRENTS; ELECTRIC INVERTERS; ELECTROSTATICS; INTEGRATED CIRCUIT TESTING; STATISTICAL METHODS; TRANSIENTS;

CURRENT INJECTION; DEVICE UNDER TEST POWER SUPPLIES; ELECTROSTATIC DISCHARGE; LATCHUP TESTING; OVERVOLTAGE; POWER SUPPLY SLEW RATE TESTS; PULSE SIMULATOR; TRANSIENT STIMULATION;

CMOS INTEGRATED CIRCUITS;

EID: 0029544242     PISSN: 07395159     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/eosesd.1995.478284     Document Type: Conference Paper

References (8)