A CMOS phase-locked loop with an auto-calibrated VCO

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 3, Issue , 2002, Pages

  Fouzar, Y ^a   Savaria, Y ^a   Sawan, M ^a  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; FREQUENCY DIVIDING CIRCUITS; INTEGRATED CIRCUIT LAYOUT; LOW PASS FILTERS; NATURAL FREQUENCIES; VARIABLE FREQUENCY OSCILLATORS;

AUTO-CALIBRATION; PHASE FREQUENCY DETECTOR; PHASE NOISE SENSITIVITY; SOFTWARE PACKAGE CADENCE;

PHASE LOCKED LOOPS;

EID: 0036287154     PISSN: 02714310     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. A study of phase noise in CMOS oscillators
2. A 2-1600 MHz CMOS clock recovery PLL with low-Vdd capability
3. A new PLL design for clock management applications
4. PLL-BiCMOS on-chip clock generator for very high-speed microprocessor
5. High-speed wide-locking range frequency calibration
6. A new controlled loop gain phase-locked loop technique
7. New CMOS small-area short-locking time and wide-locking range frequency-locked loop
8. CMOS wide-swing differential VCO for fully integrated fast PLL
9. Charge-pump phase-lock loops