A new controlled gain phase-locked loop technique

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 810-813

  Fouzar, Y ^a   Savaria, Y ^a   Sawan, M ^a  

^a ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ADAPTATION MECHANISM; CMOS TECHNOLOGY; DIFFERENTIAL VOLTAGE CONTROLLED OSCILLATORS; FREQUENCY DETECTORS; FREQUENCY DEVIATION; OPERATING VOLTAGE; PHASE FREQUENCY DETECTORS; SPECTRE SIMULATIONS;

CMOS INTEGRATED CIRCUITS; LOCKS (FASTENERS); PHASE LOCKED LOOPS;

CIRCUIT SIMULATION;

EID: 4243628347     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922361     Document Type: Conference Paper

References (9)

1. Behzad Razavi. "Monolithic Phase-Locked Loops and Clock Recovery Circuits. Theory and Design". IEEE press. 1996.
2. Y. Fouzar. M. Sawan. Y. Savaria. "A New Fully Integrated CMOS Phase-Locked Loop With Low Jitter and Fast Lock Time". IEEE International Symposium on Circuits and Systems. Geneva. 2000.
3. Joonsuk Lee. Beomsup Kim. "A 250 MHz Low Jitter Adaptive Bandwith PLL". IEEE International Solid-State Circuits Conference 1999.
4. S. Tanoi. T. Tanabe. K. Takahashi. S. Miyamoto and M. Uesugi. "A 250-622 MHz Deskew and Jitter-Suppressed Clock Buffer Using Two-Loop Architecture". IEEE JSSC. Vol. 31. NO. 4. April 1996.
5. Y. Fouzar. M. Sawan. Y. Savaria. "CMOS Wide-Swing Differential VCO for Fully Integrated Fast PLL". accepted for presentation IEEE-43rd MWSCAS Conference, Michigan, 2000.
6. A. Djemouai, M. Sawan and M. Slamani, "High Performance Integrated CMOS Frequency-to-Voltage Converter". International Conference on Microelectronics. Tunisia, pp.6366. Dec. 1998.
7. S. Tanoi. T. Tanabe, K. Takahashi, S. Miyamoto and M. Uesugi, "A 250-622 MHz Deskew and Jitter-Suppressed Clock Buffer Using Two-Loop Architecture", IEEE JSSC, Vol. 31, NO. 4, April 1996.
8. David Johns and Ken Martin, "Analog Integrated Circuit Design". 1997.
9. A. Djemouai, M. Sawan and M. Slamani, "200 MHZ frequency-locked loop based on new frequency-to-voltage converters approach". IEEE International Symposium on Circuits and Systems 2 May 30-Jun 2 1999, p II-89-11-92.