New frequency-locked loop based on CMOS frequency-to-voltage converter: Design and implementation

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 48, Issue 5, 2001, Pages 441-449

  Djemouai, Abdelouahab ^b   Sawan, Mohamad A ^a,c   Slamani, Mustapha ^d  

^a IEEE

^b Intrinsix Canada Corporation   (Canada)

^c ÉCOLE POLYTECHNIQUE DE MONTRÉAL   (Canada)

^d UNIVERSITÉ DU QUÉBEC À MONTRÉAL   (Canada)

Author keywords

Differential delay cell; Frequency locked loop; Frequency to voltage converter; Phase locked loop; Voltage controlled oscillator

Indexed keywords

CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; DESIGN; ELECTRIC CHARGE; FREQUENCY CONVERTER CIRCUITS; OPERATIONAL AMPLIFIERS; VARIABLE FREQUENCY OSCILLATORS;

CAPACITORS CHARGE REDISTRIBUTION PRINCIPLE; DIFFERENTIAL DELAY CELLS; FREQUENCY LOCKED LOOP; FREQUENCY-TO-VOLTAGE CONVERTER; SOFTWARE PACKAGE HSPICE;

PHASE LOCKED LOOPS;

EID: 0035327948     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.938354     Document Type: Article

References (7)

1. A 320 MHz, 1.5 mW @ 1.35 V CMOS PLL for microprocessor clock generation
2. A power and area efficient CMOS clock/data recovery circuit for high-speed serial interfaces
3. New circuit techniques based on a high performance frequency-to-voltage conversion
4. A 200 MHz frequency-locked loop based on new frequency-to-voltage converters approach
5. High performance integrated CMOS frequency-to-voltage converter
6. Folded source-coupled logic vs. CMOS static logic for low-noise mixed-signal IC's