A new PLL design for clock management applications

ISCAS 2001 - 2001 IEEE International Symposium on Circuits and Systems, Conference Proceedings

Volumn 4, Issue , 2001, Pages 814-817

  Brynjolfson, Ian ^a   Zilic, Zeljko ^a  

^a MCGILL UNIVERSITY   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

ACQUISITION TIME; COARSE TUNING; DYNAMIC SOFTWARES; LENGTH ADJUSTMENT; LOW-POWER DESIGN; MANAGEMENT APPLICATIONS; OPERATING RANGES; PHASE LOCKED LOOP (PLL);

CIRCUIT OSCILLATIONS; CLOCKS; DELAY CIRCUITS; JITTER; PHASE LOCKED LOOPS; VARIABLE FREQUENCY OSCILLATORS;

DESIGN;

EID: 64049118663     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/ISCAS.2001.922362     Document Type: Conference Paper

References (10)

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