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Volumn E82-C, Issue 9, 1999, Pages 1777-1779

A low-power half-swing clocking scheme for flip-flop with complementary gate and source drive

Author keywords

CMOS flip flop; Complementary drive; Half swing clocking; Low power

Indexed keywords

CMOS INTEGRATED CIRCUITS; GATES (TRANSISTOR); LOGIC GATES; VLSI CIRCUITS;

EID: 0033335149     PISSN: 09168524     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article
Times cited : (7)

References (4)
  • 1
    • 0028448788 scopus 로고
    • Power consumption estimation in CMOS VLSI chips
    • June
    • D. Liu and C. Svensson, "Power consumption estimation in CMOS VLSI chips," IEEE J. Solid-State Circuits, vol.29, no.6, pp.663-670, June 1994.
    • (1994) IEEE J. Solid-State Circuits , vol.29 , Issue.6 , pp. 663-670
    • Liu, D.1    Svensson, C.2
  • 2
    • 0029291150 scopus 로고
    • Half-swing clocking scheme for 75% power saving in clocking circuitry
    • April
    • H. Kojima, S. Tanaka, and K. Sasaki, "Half-swing clocking scheme for 75% power saving in clocking circuitry," IEEE J. Solid-State Circuits, vol.30, no.4, pp.432-435, April 1995.
    • (1995) IEEE J. Solid-State Circuits , vol.30 , Issue.4 , pp. 432-435
    • Kojima, H.1    Tanaka, S.2    Sasaki, K.3
  • 3
    • 0032070396 scopus 로고    scopus 로고
    • A reduced clock-swing flip-flop (RCSFF) for 63% power reduction
    • May
    • H. Kawaguchi and T. Sakurai, "A reduced clock-swing flip-flop (RCSFF) for 63% power reduction," IEEE J. Solid-State Circuits, vol.33, no.5, pp.807-811, May 1998.
    • (1998) IEEE J. Solid-State Circuits , vol.33 , Issue.5 , pp. 807-811
    • Kawaguchi, H.1    Sakurai, T.2


* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.