|
Volumn E82-C, Issue 9, 1999, Pages 1777-1779
|
A low-power half-swing clocking scheme for flip-flop with complementary gate and source drive
|
Author keywords
CMOS flip flop; Complementary drive; Half swing clocking; Low power
|
Indexed keywords
CMOS INTEGRATED CIRCUITS;
GATES (TRANSISTOR);
LOGIC GATES;
VLSI CIRCUITS;
COMPLEMENTARY GATE;
DELAY TIME;
HALF SWING CLOCKING;
FLIP FLOP CIRCUITS;
|
EID: 0033335149
PISSN: 09168524
EISSN: None
Source Type: Journal
DOI: None Document Type: Article |
Times cited : (7)
|
References (4)
|