An algorithm for integrated pin assignment and buffer planning

Proceedings - Design Automation Conference

Volumn , Issue , 2002, Pages 584-589

  Xiang, Hua ^a   Tang, Xiaoping ^a   Wong, D F ^a  

^a UNIVERSITY OF TEXAS AT AUSTIN   (United States)

Author keywords

Buffer insertion; Min cost maximum flow; Pin assignment

Indexed keywords

ALGORITHMS; COSTS; INTERCONNECTION NETWORKS; MICROPROCESSOR CHIPS;

INTEGRATED PIN ASSIGNMENT;

BUFFER STORAGE;

EID: 0036047787     PISSN: 0738100X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1145/513918.514067     Document Type: Conference Paper

References (12)

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5. Global wires harmful?
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7. Planning buffer locations by network flows