Simultaneous switching noise analysis and low-bounce buffer design

IEE Proceedings: Circuits, Devices and Systems

Volumn 148, Issue 6, 2001, Pages 303-311

  Jou, S J ^a   Cheng, W C ^a   Lin, Y T ^a  

^a NATIONAL CENTRAL UNIVERSITY   (Taiwan)

Author keywords

[No Author keywords available]

Indexed keywords

BUFFER CIRCUITS; CMOS INTEGRATED CIRCUITS; COMPUTER SIMULATION; INTEGRATED CIRCUIT TESTING; MOSFET DEVICES; SPURIOUS SIGNAL NOISE;

ALPHA-POWER LAW MODEL; CARRIER VELOCITY SATURATION EFFECTS; SIMULTANEOUS SWITCHING NOISE; SOFTWARE PACKAGE HSPICE;

ELECTRIC NETWORK ANALYSIS;

EID: 0035707220     PISSN: 13502409     EISSN: None     Source Type: Journal    
DOI: 10.1049/ip-cds:20010624     Document Type: Article

References (19)

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