Simultaneous switching noise analysis on bus lines using coupled circuit and electromagnetic simulation

IEEE Topical Meeting on Electrical Performance of Electronic Packaging

Volumn , Issue , 2001, Pages 203-206

  Mabuchi, Yuichi ^a   Suwa, Motoo ^a   Fukumoto, Hideshi ^a   Nakamura, Atsushi ^a  

^a HITACHI LTD   (Japan)

Author keywords

[No Author keywords available]

Indexed keywords

CHIP SCALE PACKAGES; COMPUTER SIMULATION; CROSSTALK; ELECTRIC POTENTIAL; ELECTRONICS PACKAGING; INDUCTANCE; LSI CIRCUITS; PRINTED CIRCUIT BOARDS; SPURIOUS SIGNAL NOISE;

BALL GRID ARRAY; BUS LINES; ELECTROMAGNETIC SIMULATION; LOW INDUCTANCE PACKAGE; SWITCHING NOISE ANALYSIS; WARE PROCESS PACKAGE;

PRINTED CIRCUIT DESIGN;

EID: 0035704355     PISSN: None     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (6)

1. New simultaneous switching noise analysis and modeling for high-speed and high-density CMOS IC package design
2. Modeling of simultaneous switching noise in high speed system
3. Diagnosing transmission line termination faults by means of wavelet based crosstalk signature recognition
4. Experimental verification of the use of metal filled via hole fences for crosstalk control of microstrip lines in LTCC packages
5. Inductance calculation of multiple arbitrary shaped planes using finite element integral equation method
6. SPICE2, "A computer program to simulate semiconductor circuits"