A reconfigurable Viterbi decoder architecture

Conference Record of the Asilomar Conference on Signals, Systems and Computers

Volumn 1, Issue , 2001, Pages 66-71

  Chadha, Kanu ^a   Cavallaro, Joseph R ^a  

^a RICE UNIVERSITY   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

ALGORITHMS; CELLULAR RADIO SYSTEMS; CODE DIVISION MULTIPLE ACCESS; COMPUTATIONAL COMPLEXITY; CONSTRAINT THEORY; CONVOLUTIONAL CODES; DECODING; LOCAL AREA NETWORKS; LOGIC DESIGN; PARALLEL PROCESSING SYSTEMS; SIGNAL RECEIVERS; WIRELESS TELECOMMUNICATION SYSTEMS;

ADD COMPARE SELECT; BRANCH METRIC UNIT; THIRD GENERATION SYSTEMS; VITERBI DECODER;

FIELD PROGRAMMABLE GATE ARRAYS;

EID: 0035573082     PISSN: 10586393     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/acssc.2001.986882     Document Type: Conference Paper

References (8)

1. Locally connected VLSI architectures for the Viterbi algorithm
2. RACER: A reconfigurable constraint length 14 Viterbi decoder
3. Architecture selection for a low power flexible Viterbi decoder
4. Low-power bit-serial Viterbi decoder for 3rd generation W-CDMA systems
5. Viterbi decoding techniques in the TMS320C54x family
6. Generalized traceback techniques for survivor memory management in the Viterbi algorithm
7. A reconfigurable decoder architecture for wireless LAN and cellular systems