Architecture selection for a low power flexible Viterbi decoder

Proceedings - IEEE International Conference on Third Generation Wireless Communications

Volumn , Issue , 2000, Pages 223-230

  Hocevar, Dale ^a   Gatherer, Alan ^a  

^a TEXAS INSTRUMENTS   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOW POWER FLEXIBLE VITERBI DECODER; VITERBI DECODING; VOICE CHANNELS; WIRELESS CELLULAR APPLICATIONS;

BANDWIDTH; COMPUTER ARCHITECTURE; DATA STORAGE EQUIPMENT; DECODING; DIGITAL SIGNAL PROCESSING; WIRELESS TELECOMMUNICATION SYSTEMS;

COMPUTER HARDWARE;

EID: 23844468917     PISSN: 15292592     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (9)

1. rd Edition," McGraw Hill, New York, 1995.
2. P.O. Gulak and E. Shwedyk, "VLSI structures for Viterbi receivers: Part I - General theory and applications," IEEE J. on Selected Areas in Comm., vol. SAC-4, no. 1, pp. 142-154, January 1986.
3. P.G. Gulak and T. Kailath, "Locally connected VLSI architectures for the Viterbi algorithm," IEEE J. Selected Areas in Comm., vol. 6, no. 3, pp. 527-537, April 1988.
4. C.B. Shung, H.-D. Lin, R. Cypher, P.H. Siegel, and H.K. Thapar, "Area-Efficient Architectures for the Viterbi Algorithm - Part I: Theory," IEEE Trans. On Comm., vol. 41, no. 4, pp. 636-644, April 1993.
5. P. Black, "Algorithms and architectures for high speed Viterbi decoding," Ph.D. Dissertation, Dept. of Elec. Eng., Stanford University, Stanford, CA, 1993.
6. G. Feygin, P.G. Gulak and P. Chow, "A multiprocessor architecture for Viterbi decoders with linear speedup," IEEE Trans. on Signal Proc., vol. 41, no. 9, pp. 2907-2917, September 1993.
7. J. Sparsø, H.N. Jørgensen, E. Paaske, S. Pedersen, and T. Rübner-Petersen, "An area-efficient topology for VLSI implementation of Viterbi decoders and other shuffle-exchange type structures," IEEE J. Solid-State Circuits, vol. 26, no. 2, pp. 90-97, February 1991.
8. E. Paaske, S. Pedersen, and J. Sparsø, "An area-efficient path memory structure for VLSI implementation of high speed Viterbi decoders," INTEGRATION, the VLSI journal, (Elsevier Science Publishers), vol. 12, pp. 79-91, 1991.
9. R. Cypher and C.B. Shung, "Generalized trace back techniques for survivor memory management in the Viterbi algorithm," IEEE GLOBECOM, pp. 1318-1322, December 1990.