RACER: A reconfigurable constraint-length 14 Viterbi decoder

IEEE Symposium on FPGAs for Custom Computing Machines, Proceedings

Volumn , Issue , 1996, Pages 60-69

  Yeh, David ^a   Feygin, Gennady ^a   Chow, Paul ^a  

^a UNIVERSITY OF TORONTO   (Canada)

Author keywords

[No Author keywords available]

Indexed keywords

APPLICATION SPECIFIC INTEGRATED CIRCUITS; COMPUTER ARCHITECTURE; DIGITAL COMMUNICATION SYSTEMS; INTEGRATED CIRCUIT LAYOUT; LOGIC GATES; MICROPROCESSOR CHIPS;

CONSTRAINT LENGTH VITERBI DECODER; FIELD PROGRAMMABLE GATE ARRAYS (FPGA);

DECODING;

EID: 0030410149     PISSN: 10823409     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/fpga.1996.564746     Document Type: Conference Paper

References (27)