Electrical performance improvements on RFICs using bump chip carrier packages as compared to standard thin shrink small outline packages

IEEE Transactions on Advanced Packaging

Volumn 24, Issue 4, 2001, Pages 548-554

  Horng, Tzyy Sheng ^a,b   Wu, Sung Mao ^b   Chiu, Chi Tsung ^c   Hung, Chih Pin ^c  

^a IEEE   (Taiwan)

^b NATIONAL SUN YAT SEN UNIVERSITY   (Taiwan)

^c ADVANCED SEMICONDUCTOR ENGINEERING INC   (Taiwan)

Author keywords

Bump chip carrier packages; Heterojunction bipolar transistors; Monte Carlo analysis; RFIC packages; Think shrink small outline packages

Indexed keywords

BUMP CHIP CARRIER PACKAGE; GAUSSIAN DISTRIBUTION; RADIO FREQUENCY INTEGRATED CIRCUIT; THIN SHRINK SMALL OUTLINE PACKAGE;

COMPUTER SIMULATION; HETEROJUNCTION BIPOLAR TRANSISTORS; INTEGRATED CIRCUIT LAYOUT; MATHEMATICAL MODELS; MICROSTRIP LINES; MICROWAVE INTEGRATED CIRCUITS; MONTE CARLO METHODS; POWER AMPLIFIERS; PRINTED CIRCUIT BOARDS; SCATTERING PARAMETERS; SEMICONDUCTING GALLIUM ARSENIDE; SURFACE MOUNT TECHNOLOGY;

ELECTRONICS PACKAGING;

EID: 0035521104     PISSN: 15213323     EISSN: None     Source Type: Journal    
DOI: 10.1109/6040.982843     Document Type: Article

References (8)

1. Method of producing a semiconductor device having a lead portion with outer connecting terminal
2. Semiconductor device and method for manufacturing semiconductor device
3. Measurement and field simulation based characterization of plastic packages
4. Electrical modeling of RFIC packages up to 12 GHz
5. Advanced measurement techniques for generation of SPICE models of RFIC packages
6. Heterojunction bipolar transistors and integrated circuits
7. GaAs heterojunction bipolar transistor device and IC technology for high-performance analog and microwave applications