SCOPUS 정보 검색 플랫폼

Journal of Electronic Testing: Theory and Applications (JETTA)

Volumn 17, Issue 5, 2001, Pages 395-408

Frequency response verification of analog circuits using global optimization techniques

(2) Seshadri, Suresh a Abraham, Jacob A a

a The University of Texas at Austin (United States)

Author keywords

Analog circuits; Formal techniques; Frequency response; Global optimization; Modeling; Parameter variation; Verification

Indexed keywords

COMPUTER SIMULATION; DIGITAL CIRCUITS; FORMAL LOGIC; FREQUENCY RESPONSE; GLOBAL OPTIMIZATION; LINEAR NETWORK SYNTHESIS; LOGIC CIRCUITS; MATHEMATICAL MODELS;

ANALOG CIRCUITS; FORMAL TECHNIQUE; VERIFICATION PROBLEM;

LINEAR NETWORK ANALYSIS;

EID: 0035492147 PISSN: 09238174 EISSN: None Source Type: Journal
DOI: 10.1023/A:1012751118746 Document Type: Article

Times cited : (4)

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* 이 정보는 Elsevier사의 SCOPUS DB에서 KISTI가 분석하여 추출한 것입니다.