Multiple gate delay fault diagnosis using test-pairs for marginal delays

IEICE Transactions on Information and Systems

Volumn E81-D, Issue 7, 1998, Pages 706-715

  Boateng, Kwame Osei ^a   Takahashi, Hiroshi ^a   Takamasu, Yuzo ^a  

^a EHIME UNIVERSITY   (Japan)

Author keywords

Combinational circuit; Diagnostic rules; Fault diagnosis; Multiple delay fault; Path tracing method; Test pairs for marginal delays

Indexed keywords

GATES (TRANSISTOR); INTEGRATED CIRCUIT TESTING;

MULTIPLE GATE DELAY FAULT DIAGNOSIS; PATH-TRACING METHODS;

COMBINATORIAL CIRCUITS;

EID: 0032120335     PISSN: 09168532     EISSN: None     Source Type: Journal    
DOI: None     Document Type: Article

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