A low-power array multiplier using separated multiplication technique

IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing

Volumn 48, Issue 9, 2001, Pages 866-871

  Han, C Y ^a   Park, H J ^a   Kim, L S ^a  

^a Korea Advanced Institute of Science and Technology (KAIST)   (South Korea)

Author keywords

FIR filter; Low power; LRU; Multiplier

Indexed keywords

CACHE MEMORY; CALCULATIONS; FIR FILTERS; IMAGE PROCESSING; MULTIPLYING CIRCUITS; TWO DIMENSIONAL; WAVELET TRANSFORMS;

DIFFERENTIAL COEFFICIENTS METHOD; DISCRETE WAVELET TRANSFORM; LOW-POWER ARRAY MULTIPLIER; SEPARATED MULTIPLICATION TECHNIQUE;

DIGITAL SIGNAL PROCESSING;

EID: 0035456158     PISSN: 10577130     EISSN: None     Source Type: Journal    
DOI: 10.1109/82.965002     Document Type: Article

References (13)

1. Minimizing power consumption in digital CMOS circuits
2. Design and implementation of a 16 by 16 low-power two's complement multiplier
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8. Low power FIR filter realizations with differential coefficients and inputs
9. Decorrelating (DECOR) transforms for low-power digital filters
10. Semi-recursive VLSI architecture for two dimensional discrete wavelet transform
11. Orthonormal bases if compactly supported wavelets