Design and implementation of a 16 by 16 low-power two's complement multiplier

Proceedings - IEEE International Symposium on Circuits and Systems

Volumn 5, Issue , 2000, Pages V-345-V-348

  Goldovsky, Alexander ^a   Patel, Bimal ^a   Schulte, Michael ^a,b   Kolagotla, Ravi ^a,c   Srinivas, Hosahalli ^a   Burns, Geoffrey ^a,d  

^a NOKIA RESEARCH CENTER   (United States)

^b LEHIGH UNIVERSITY   (United States)

^c INTEL CORPORATION   (United States)

^d PHILIPS RESEARCH LABORATORIES   (Netherlands)

Author keywords

[No Author keywords available]

Indexed keywords

EID: 85013249651     PISSN: 02714310     EISSN: None     Source Type: Journal    
DOI: 10.1109/ISCAS.2000.857435     Document Type: Article

References (21)

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