A pipelined architecture for the multidimensional DFT

IEEE Transactions on Signal Processing

Volumn 49, Issue 9, 2001, Pages 2096-2102

  Yu, Sungwook ^b   Swartzlander Jr , Earl E ^a,c  

^a IEEE

^b INTEL CORPORATION   (United States)

^c The University of Texas at Austin   (United States)

Author keywords

Discrete Fourier transform; Multidimensional transforms; Pipelined architecture

Indexed keywords

ALGORITHMS; COMPUTER ARCHITECTURE; DISCRETE FOURIER TRANSFORMS; PIPELINE PROCESSING SYSTEMS; SYSTOLIC ARRAYS;

PIPELINED ARCHITECTURE;

DIGITAL SIGNAL PROCESSING;

EID: 0035447437     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/78.942637     Document Type: Article

References (16)

1. VLSI architectures for multidimensional Fourier transform processing
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6. An algorithm for the machine calculation of complex Fourier series
7. Index mappings for multidimensional formulation of the DFT and convolution
8. Parallelism in fast Fourier transform hardware
9. Systolic FFT processors
10. Pipelined adders
11. A radix 4 delay commutator for fast Fourier transform processor implementation
12. A radix-8 wafer scale FFT processor
13. A chip set for pipeline and parallel pipeline FFT architectures
14. Implementation of the FFT butterfly with redundant arithmetic