Multidimensional systolic arrays for the implementation of discrete Fourier transforms

IEEE Transactions on Signal Processing

Volumn 47, Issue 5, 1999, Pages 1359-1370

  Lim, Hyesook ^a,b   Swartzlander Jr , Earl E ^c  

^a IEEE

^b LUCENT TECHNOLOGIES   (United States)

^c The University of Texas at Austin   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COMPUTATIONAL METHODS; DATA PROCESSING; FAST FOURIER TRANSFORMS; MULTIPLEXING EQUIPMENT; MULTIPLYING CIRCUITS; ONE DIMENSIONAL; TWO DIMENSIONAL;

MULTIDIMENSIONAL DISCRETE FOURIER TRANSFORMS; PRIME FACTOR COMPUTATION;

SYSTOLIC ARRAYS;

EID: 0032684240     PISSN: 1053587X     EISSN: None     Source Type: Journal    
DOI: 10.1109/78.757223     Document Type: Article

References (17)

1. I. Gertner and M. Shamash "VLSI architectures for multidimensional Fourier transform processing" IEEE Trans. Comput. vol. C-36 pp. 1265-1274 1987.
2. E. E. Swartzlander Jr. "Systolic EFT processors" in Systolic Arrays W. Moore A. McCabe and R. Urquhart Eds. Boston MA: Adam Hilger 1987 pp. 133-140.
3. J. O'Brien J. Mather and B. Holland "A 200 MIPS single-chip IK FFT processor" in IEEE Int. Solid-State Circuits Conf. Rec. 1989 pp. 166-167.
4. S. Magar S. Shen G. Luikuo M. Fleming and R. Agular "An application specific chipset for 100 MHz data rate" in Proc. Int. Conf. Acoust. Speech Signal Process. 1988 pp. 1989-1992.
5. A. V. Oppenheim and R. W. Schafer Discrete-Time Signal Processing. Englewood Cliffs NJ: Prentice-Hall 1989 ch. 9.
6. E. E. Swartzlander Jr. VLSI Signal Processing Systems. Boston MA: Kluwer 1986 ch. 6.
7. T. D. Roziner and M. G. Karpovsky "Multidimensional Fourier transforms by systolic architectures" J. VLSI Signal Process. vol. 4 pp. 343-354 1992.
8. M. H. Lee "High speed multidimensional systolic arrays for discrete Fourier transform" IEEE Trans. Circuits Syst. II vol. 39 pp. 876-879 1992.
9. C. N. Zhang and D. Y. Y. Yun "Multi-dimensional systolic networks for discrete Fourier transform" in Proc. 11th Int. Symp. Comput. Architecture Ann Arbor MI 1984 pp. 215-222.
10. J. A. Beraldin T. Aboulnasr and W. Steenaart "Efficient one-dimensional systolic array realization of the discrete Fourier transform" IEEE Trans. Circuits Syst. vol. 36 pp. 95-100 1989.
11. J. Canaris "A VLSI architecture for the real time computation of discrete trigonometric transforms" J. VLSI Signal Process. vol. 5 pp. 95-104 1993.
12. M. Sheu J. Lee J. Wang A. Suen and L. Liu "A high throughput-rate architecture for 8*8 2-D DCT" in Proc. IEEE Int. Symp. Circuits Syst. 1993 vol. 3 pp. 1587-1590.
13. S. Y. Kung VLSI Array Processors. Englewood Cliffs NJ: Prentice-Hall 1988.
14. H. S. Lim and E. E. Swartzlander Jr. "Multidimensional systolic arrays for multidimensional DFT's" in Proc. Int. Conf. Acoust. Speech Signal Process. 1996 pp. 3277-3280.
15. C. S. Burrus "Index mappings for multidimensional formulation of the DFT and convolution" IEEE Trans. Acoust. Speech Signal Processing vol. ASSP-25 pp. 239-242 1977.
16. I. Nivenand H. S. Zuckerman An Introduction to the Theory of Numbers 3rd ed. New York: Wiley 1972 ch. 2.
17. C. D. Thompson "Fourier transforms in VLSI" IEEE Trans. Comput. vol. C-32 pp. 1047-1057 1983.