Performance optimization under rise and fall parameters

IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers

Volumn , Issue , 1999, Pages 185-190

  Murgai, Rajeev ^a  

^a FUJITSU LABORATORIES OF AMERICA   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

LOGIC CIRCUITS; LOGIC GATES; MATHEMATICAL MODELS; POLYNOMIALS; TOPOLOGY;

BUFFER INSERTION; CELL PARAMETERS; FIXED TOPOLOGY NET; LOAD INDEPENDENT DELAY MODEL; POLYNOMIAL TIME COMPLEXITIES; RISE AND FALL PARAMETERS;

ALGORITHMS;

EID: 0033343887     PISSN: 10923152     EISSN: None     Source Type: Conference Proceeding    
DOI: None     Document Type: Conference Paper

References (15)