Efficient edge profiling for ILP-processors

Parallel Architectures and Compilation Techniques - Conference Proceedings, PACT

Volumn , Issue , 1998, Pages 294-303

  Eichenberger, Alexandre E ^a   Lobo, Sheldon M ^a  

^a North Carolina State University   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

CODES (SYMBOLS); COST REDUCTION; EMBEDDED SYSTEMS; PARALLEL ARCHITECTURES;

CODE LAYOUT; DYNAMIC APPLICATIONS; EDGE PROFILING; INSTRUCTION LEVEL PARALLELISM; INSTRUCTION SCHEDULING; INSTRUMENTATION CODE; PROFILING INFORMATIONS; SUPERSCALAR;

VERY LONG INSTRUCTION WORD ARCHITECTURE;

EID: 77952766622     PISSN: 1089795X     EISSN: None     Source Type: Conference Proceeding    
DOI: 10.1109/PACT.1998.727264     Document Type: Conference Paper

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