Yield and cost model for integrated optical chips

Journal of Lightwave Technology

Volumn 14, Issue 2, 1996, Pages 158-163

  März, Reinhard ^a,b,c   Mahlein, Hans F ^a,c,d,e   Acklin, Bruno ^a,f,g,h  

^a SIEMENS AG   (Germany)

^b GOETHE UNIVERSITY   (Germany)

^c Research Laboratories of Siemens AG ^*

^d TECHNICAL UNIVERSITY OF MUNICH   (Germany)

^e Ctrl Labs Telecom Grp S

^f ETH ZURICH   (Switzerland)

^g UNIVERSITY OF NEUCHÂTEL   (Switzerland)

^h LUCENT TECHNOLOGIES   (United States)

Author keywords

[No Author keywords available]

Indexed keywords

COSTS; INTEGRATED CIRCUIT MANUFACTURE; LARGE SCALE SYSTEMS; MATHEMATICAL MODELS; STATISTICAL METHODS;

INTEGRATED OPTICAL CHIPS; YIELD MODELING;

INTEGRATED OPTOELECTRONICS;

EID: 0030084489     PISSN: 07338724     EISSN: None     Source Type: Journal    
DOI: 10.1109/50.482257     Document Type: Article

References (5)

1. S. M. Hu, "Some considerations in the formulation of IC yield statistics," Solid State Electron., vol. 22, pp. 205-211, 1979.
2. C. H. Stapper, "Large-area fault clusters and fault tolerance in VLSI circuits: A review," IBM J. Res. Develop., vol. 33, pp. 162-173, 1989.
3. U. Ramacher, "A cost oriented redundancy model for defect-tolerant VLSI/WSI systems," in Yield Modeling and Statistics Bristol, England: Hilger, 1987, pp. 233-245.
4. M. De Bortoli, M. De Padova, R. H. Lord and A. Moncalvo, "Economic evaluation of optoelectronic integration for optical broadband subscriber loop," in Proc. ECOC'89, 1989, vol. 3, pp. 120-127.
5. R. J. Schuelke and K. P. Pande, "Manufacturing cost analysis of optoelectronic integrated circuits," IEEE Trans. Semiconduct. Manufact., vol. 2, pp. 29-30, 1989.